TLC2264AMJ
OP Amp Quad GP R-R O/P ±8V/16V 14-Pin CDIP Tube
廠商型號(hào):
TLC2264AMJ
芯天下內(nèi)部編號(hào):
136-TLC2264AMJ
生產(chǎn)廠商:
texas instruments
描述:
OP Amp Quad GP R-R O/P ±8V/16V 14-Pin CDIP Tube
產(chǎn)品類別:
Amplifiers|OP Amp
客戶編號(hào):
規(guī)格書:
查看PDF
所示圖像僅為示意圖。請(qǐng)從產(chǎn)品數(shù)據(jù)表中獲得準(zhǔn)確的規(guī)格。
庫(kù)存與訂購(gòu)
產(chǎn)品參數(shù)
| 參數(shù)類型 | 參數(shù)值 |
|---|---|
| Package | 14CDIP |
| Number of Channels per Chip | 4 |
| Type | General Purpose Amplifier |
| Typical Gain Bandwidth Product | 0.71 MHz |
| Typical Slew Rate | 0.55@5V V/us |
| Rail to Rail | Rail to Rail Output |
| Maximum Supply Current | 1@5V mA |
| Maximum Input Offset Voltage | 0.95@±2.5V mV |
| Maximum Input Bias Current | 0.000001(Typ)@±2.5V uA |
| Typical Input Noise Voltage Density | 40@5V nV/rtHz |
| Minimum CMRR | 70 dB |
| Minimum Single Supply Voltage | 4.4 V |
| Maximum Single Supply Voltage | 16 V |
| Minimum Dual Supply Voltage | ±2.2 V |
| Maximum Dual Supply Voltage | ±8 V |
| Mounting | Through Hole |
| Operating Temperature | -55 to 125 °C |
| Typical NonInverting Input Noise Current Density | 0.0006@5V pA/rtHz |
| Typical Voltage Gain | 114.81 dB |
| Standard Package | Rail / Tube |
| Manufacturer Type | Low Noise Amplifier |
| Typical Single Supply Voltage | 5|9|12|15 |
| Package Width | 7.62(Max) |
| PCB | 14 |
| Maximum Power Dissipation | 1375 |
| Maximum Dual Supply Voltage | ±8 |
| Maximum Input Bias Current | 0.000001(Typ)@±2.5V |
| Maximum Supply Current | 1@5V |
| Typical Gain Bandwidth Product | 0.71 |
| Typical Voltage Gain | 114.81 |
| Power Supply Type | Single|Dual |
| Output Type | CMOS|Rail to Rail |
| Minimum CMRR | 70 |
| Minimum Operating Temperature | -55 |
| Supplier Package | CDIP |
| Standard Package Name | CDIP |
| Maximum Operating Temperature | 125 |
| Maximum Single Supply Voltage | 16 |
| Minimum Dual Supply Voltage | ±2.2 |
| Typical Dual Supply Voltage | ±3|±5 |
| Shut Down Support | No |
| Package Length | 19.94(Max) |
| Pin Count | 14 |
| Maximum Input Offset Current | 0.0000005(Typ)@±2.5V |
| Maximum Input Offset Voltage | 0.95@±2.5V |
| Minimum Single Supply Voltage | 4.4 |
| Package Height | 3.56(Max) |
| Packaging | Tube |
| Typical Slew Rate | 0.55@5V |
| Technology | LinCMOS |
| Lead Shape | Through Hole |
| Input Offset Voltage | 0.95 mV |
| Power Dissipation | 1.375 W |
| Operating Temp Range | -55C to 125C |
| Package Type | CDIP |
| Number of Elements | 4 |
| Common Mode Rejection Ratio | 70 dB |
| Operating Temperature Classification | Military |
| Dual Supply Voltage (Typ) | ?3/?5 V |
| Input Bias Current | 0.001 nA |
| Slew Rate | 0.55 V/us |
| Power Supply Requirement | Single/Dual |
| Dual Supply Voltage (Min) | ?2.2 V |
| Rail/Rail I/O Type | Rail to Rail Output |
| Shut Down Feature | No |
| Rad Hardened | No |
| Single Supply Voltage (Min) | 4.4 V |
| Single Supply Voltage (Max) | 16 V |
| Single Supply Voltage (Typ) | 5/9/12/15 V |
| Dual Supply Voltage (Max) | ?8 V |
| Voltage Gain in dB | 114.81 dB |
| Unity Gain Bandwidth Product | 0.71MHz |
| Status | ACTIVE |
| Temp (oC) | -55 to 125 |
| DSCC # | |
| Package | Pins | CDIP?(J) | 14 |
| Device Marking | View |
| Package QTY | Carrier | 1 | TUBE |
| New Flag | |
| Functional Diagram | |
| CMRR | 70 |
| GBW | 0.82 |
| Reference Design | |
| HiRel | Y |
| Package Group | CDIP LCCC |
| BW @ Acl | |
| Vs | 16 |
| Number of Channels | 4 |
| Iib | |
| Additional Features | |
| Rail-to-Rail | Out |
| Operating Temperature Range | -55 to 125 |
| IIB | 800 |
| Datasheet | SLOS177D |
| Architecture | |
| Vn at Flatband | |
| Iq per channel | 0.25 |
| TI Design | |
| Vos (Offset Voltage @ 25C) | 0.95 |
| Rating | Military |
| Offset Drift | 2 |
| Vn at 1kHz | 12 |
| Total Supply Voltage | 4.4 |
| Acl, min spec gain | |
| Settling Time (01%) | |
| Offset Voltage Drift (+/-) | |
| Io |
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